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LC2 - SCI Link Controller for System Area Networks

The Dolphin SCI Link Controller Chip (LC2) is the leading implementation of the ANSI/IEEE Scalable Coherent Interface standard with duplex bandwidth of 500 MByte/s. The LC2 is designed to meet the system area network requirements in ccNUMA servers, high availability server clusters and remote I/O subsystems. Based on CMOS processing technology and LVDS signaling, the LC2 is an economical, reliable and powerful link interface for high performance applications. LC2 guarantees delivery of SCI packets with payloads up to 64 bytes of data. Internal buffers allow for pipelining of packets for high throughput operation, yet supports virtual cut-through routing for low latency access. Two unidirectional 16-bit LVDS links transmit data at 500 Mbytes/s over a backplane or a cable. A backside link interface (Blink™) allows a companion controller ASIC to easily connect to the LC2. The LC supports both message passing controllers (such as the Dolphin PSB chip) and cache coherence controllers (such as the Dolphin SCC chip). Multiple LCs can also communicate on the same BLink thus enabling construction of switches and counter rotating rings. Features and Benefits 500 MBytes/s Duplex link bandwidth for high performance applications Low latency, 48 ns bypass latency ANSI/IEEE 1596-1992 Scalable Coherent Interface (SCI) standard compliant ANSI/IEEE 1212 Computer Status Register (CSR) support ANSI/IEEE 1159.1 (JTAG) support Low voltage differential (LVDS) link signaling for low power, reliability and noise immunity Built-in RAS features for guaranteed data delivery, error detection, recovery and hot pluggable links 64-bit, 100 MHz LVTTL Blink™ interface

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